`include"../../src/AddImm.v"
`timescale 1ps/1ps

module testAddImm;
    reg clk, reset;
    initial clk = 1;
    always #5 clk = ~clk;

    reg[31:0] PC;
    reg[63:0] Imm_64;

    wire[31:0] Sum;

    initial 
    begin
        #10 
        PC = 32'd10;
        Imm_64 = 64'd20;

        #10
        PC = 32'd11;
        Imm_64 = 64'd21;

        #10 $stop;
    end

    AddImm U0(clk, reset, PC, Imm_64, Sum);

    initial
    begin
        $dumpfile("test.lxt");
        $dumpvars;

    end

endmodule